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Tech SPOT

 

TechSTAGNORTH  

Date: Wednesday, Dec.13 - Friday, Dec 15 10:20-16:50
Venue: Tokyo Big Sight

TechSPOT  
(East Hall 4)

TechSPOT WEST 
(East Hall 1)

TechSPOT INNOVATION&IOT
(East Hall 3)

 

Explore in-depth information of products and technologies beyond the booth at exhibitor presentations available in the Exhibitor Seminar Rooms and on TechSPOT stages on the show floor. Participation in all the seminars is free.

 

 

Exhibiting company

 

TechSPOT
(East Hall 4)

 Schedule

 

Company Name Title
OTSUKA ELECTRONICS CO., LTD. For the semiconductor's process, Otsuka Electronics Company propose the all solution method by film thickness measurement
Connectec Japan 「IoT/IoE semiconductor assembly innovation by ultra-low temperature flip-chip bonding.」
Minimal Fab Strategy Digest of Minimal Fab Development
Hitachi High-Technologies Corp Matching methodology for CD-SEM.
Korean Free Economic Zones (KFEZ) Korean semiconductor industry trend and investment environment
Minimal Fab Application Examples for Making Devices using Minimal Fab
CONNECTEC JAPAN Corporation 「An approach to low temperature bonding process for IoT/IoE device and FHE assembly.」
Hakuto Co.,Ltd. Veeco's Wafer Thinning Wet Process for Advanced Packaging Applications
Hitachi High-Technologies Corp ‘’Mirelis’’ for non-destructive inspection of crystal defects and latent scratches in SiC wafers.
HORIBA, Ltd. Next generation semiconductor process evaluation with our non-contact optical technology
TUV Rheinland Japan Ltd. Comparison on the requirements of electrical standards by the SEMI Guidelines
EVGroup Japan K.K. Latest Wafer Bonding Technologies - A Game Changer for IoT and AI
Edwards Safely Managing Dielectric CVD Process Tool Exhausts for Minimum Cost
SAFE TECHNO LIMITED Safety Design Update
Hitachi High-Technologies Corp Matching methodology for CD-SEM.
HORIBA STEC, Co., Ltd. Reduction in downtime of production equipment useful at the site and prolongation of lifetime.
Photo electron Soul Inc. The next generation metrology, inspection, and writing: Our e-beam resolves the traditional issues for productivity and performance
Tektronix Japan/Keithley Japan Lower test cost for power SEMI wafers by enabling safe, single pass test at voltages up to 3kV

 

TechSPOT WEST
(East Hall 1)

 Schedule

 

 

TechSPOT INNOVATION&IOT
(East Hall 3)

 Schedule

 

 

ATTENTION : No Interpretation Available

Please note that using English is recommended for presentation materials,
but some presentation materials are written in Japanese.

 


Question ?

SEMICON Japan Show Management Support (Sakura International Inc.)
Tel : +81-50-5804-1281
*Available Mon - Fri (except holidays) from 9:30 a.m. - Noon/1:00 p.m. - 5:00 p.m. (local time)
Email : semicon@sakurain.co.jp

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